1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming an multi-layered .alpha.-Silicon gate structure which inhibits the penetration of ions into the underlying gate oxide in the fabrication of integrated circuits.
2) Description of the Prior Art
In the fabrication of semiconductor integrated circuits, it is a conventional process to use a polysilicon gate. The polysilicon is grown at a temperature of about 620.degree. C. until the desired thickness is reached. Since the temperature is held constant throughout the growth of the polysilicon, the polysilicon grains will be column-like. FIGS. 1 and 2 illustrate a partially completed integrated circuit of the prior art in which a layer of silicon oxide 12 has been grown on a semiconductor substrate. Polysilicon layer 14 has been grown at a constant temperature of 620.degree. C., as described above.
Below the ion channel is explained. In FIG. 1, when B+ or BF.sub.2+ ions are implanted 16 into the polysilicon layer 14, the B+ ions easily diffuse through the column-like grain boundaries of the polysilicon into the gate oxide layer 12. BF.sub.2 implanted into the gate during P+ S/D I/I and annealed. Similarly, in FIG. 2, when the polysilicon layer 14 is capped with a tungsten silicide film 18, F- ions (from reactants e.g., WF.sub.6) easily diffuse through the column-like grain boundaries of the polysilicon into the gate oxide layer 12. As a consequence of this diffusion, the gate oxide effective thickness will be increased. Also, especially in the case illustrated by FIG. 2, electron traps are created within the gate oxide layer. The B+ penetration will cause threshold voltage shift causing device and circuit failure.
The present invention uses a multiple layer amorphous silicon (.alpha.-Si) gate with mismatched grain boundaries to confine the ions within the amorphous silicon (a-Si) and inhibit the penetration of the ions into the underlying gate oxide.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,518,958 (Giewont) shows a method of forming a Nitrogen--enriched doped polysilicon layer.
U.S. Pat. No. 5,482,895 (Hayashi) shows a method for forming a silicide electrode.
U.S. Pat. No. 4,797,108 (Crowther) shows an a-Si FET and implanting into the gate.
U.S. Pat. No. 4,789,883 (Cox et al.) shows an a-Si floating gate that is I/I with n-type impurities.
U.S. Pat. No. 4,597,159 (Usami) shows a method of forming a EEPROM having an a-Si gate.
U.S. Pat. No. 4,479,83 (Sandow) shows a gate formed using an a-Si layer that is annealed.
U.S. Pat. No. 5,652,156 (Liao et al.) shows a polysilicon deposition method for a gate.